The address decoder section consists of an 8-bit comparator 74LS688, a
74LS02 containing 4 NOR gates and a 74LS139 containing 2 2-to-4 decoders
(A and B). The address lines SA2-SA9
constitute an 8-bit input byte compared by the 74LS688 to a second
byte determined by an 8-fold dipswitch. This selects the base
of the 4-byte I/O address space of the card. It can be $0, $4, $8, $C etc.
The addresses $300-$31F are reserved for a prototype card. The base address
$300 (binary 11,0000,0000) is selected with bits 1100,0000 for connections
1,2,…,8 of the dip-switch. In the remainder this base address
will be assumed. The enable input #math12##tex2html_wrap_inline771# of the comparator is
connected to the AEN line. This accomplishes that the card is not selected
during DMA transfers.
On selection of one of the addresses $300 … $303 the 74LS688 output
#math13##tex2html_wrap_inline774# becomes low. This line is input to the two NOR gates
A and B of the 74LS02. The truth table of a NOR gate is:
<#792#>Table<#792#>:
<#793#>NOR gate truth table<#793#>
| X |
Y |
#math14##tex2html_wrap_inline776# |
| 0 |
0 |
1 |
| 0 |
1 |
0 |
| 1 |
0 |
0 |
| 1 |
1 |
0 |
|
A NOR gate with X=Y acts like an inverter. It follows that the enable
#math15##tex2html_wrap_inline796# of the A-part (B-part) of the decoder 74LS139 is
low when both inputs of 74LS02A(B) are low. This happens when one of the
addresses $300 … $303 is selected, while at the same time
#math16##tex2html_wrap_inline799# (#math17##tex2html_wrap_inline801#) is low. Because SA0 and SA1
are connected to the A and B inputs of the decoders, #math18##tex2html_wrap_inline803#,#tex2html_wrap_inline804#,#tex2html_wrap_inline805# or #math19##tex2html_wrap_inline807# of the
74LS139A(B) will become low during an I/O read (write) operation on
$300 … $303, respectively. So only one of the eight
decoder outputs is low at a time. The remaining seven output are high.